A method in which a BIST (Built-In Self Test) circuit is used is well known as the method for testing the semiconductor memory device, such as RAM, that is built in a semiconductor integrated circuit such as LSI (Large Scale Integration) (for example, see Japanese Patent Publication Laid-Open Nos. 2006-4509, 2002-32998, and 11-65872). Such method is hereinafter appropriately referred to as “BIST testing.” The BIST circuit is built in the semiconductor integrated circuit in advance. The BIST circuit includes a data generation circuit that automatically produces a test pattern, and a comparison circuit that compares an expected value and an output from the semiconductor memory device. In the BIST testing, the expected value and the output data from the semiconductor memory device into which the test pattern produced by the data generation circuit are compared, and a test result indicating whether or not a defect is occurred in the semiconductor memory device is supplied to an LSI tester or the like based on a result of the comparison.
Another method in which a scan test circuit including plural scan flip-flops forming a scan path or a scan chain is used is well known as the method for testing the semiconductor memory device (for example, see Japanese Patent Publication Laid-Open Nos. 2006-4509 and 2002-32998). Such method is hereinafter appropriately referred to as “scan test.” The scan test circuit is built in the semiconductor integrated circuit in advance. In the scan test, after the test pattern supplied from the outside of the semiconductor memory device is retained by an input-side scan flip-flop of the semiconductor memory device through the scan path, the test pattern is fed into the semiconductor memory device. Further, the output data from the semiconductor memory device is retained by an output-side scan flip-flop of the semiconductor memory device. Thus, determination whether or not the defect is generated semiconductor memory device is made by taking out the output data retained by the scan flip-flop to the outside through the scan path.
In the BIST testing, the data pattern is automatically produced by the BIST circuit, more specifically by the data generation circuit forming a part of the BIST circuit, so that the semiconductor memory device can be tested for a shorter time then that of the scan test. However, because the BIST testing is limited to a range of the test pattern automatically produced by the BIST circuit, various tests of the semiconductor memory device are hardly performed compared with the scan test, in which any test pattern can externally be fed into the semiconductor memory device.
In other words, in the scan test, although any test pattern can be fed into the semiconductor memory device from the outside, many test patterns are hardly fed into the semiconductor memory device to perform the test compared with the BIST testing in which the test pattern is automatically produced.
On the other hand, in the test circuit that is built in the semiconductor integrated circuit to test the semiconductor memory device, desirably a circuit area or a circuit size of the test circuit is reduced as much as possible.
In view of the foregoing, an object of embodiments of the invention is to provide a semiconductor device that can perform both the BIST testing and the scan test without increasing the circuit area.